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浙江祥新电子有限公司
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128-bit wide interface/accelerator enables high-speed 60 MHz operation.
u 32 kB to 40 kB of on-chip static RAM and 512 kB of on-chip flash memory.
n U* 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.
u An additional 8 kB of on-chip RAM accessible to U* by DMA (LPC2158 only).
n 32 segment ´ 4 backplane LCD controller supports from 1 to 4 backplanes.
n Single 10-bit DAC provides variable *og output.
n Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities.
n High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
n 100-pin LQFP package with 38 microcontroller I/O pins minimum.
n Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
u 32 kB to 40 kB of on-chip static RAM and 512 kB of on-chip flash memory.
n U* 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.
u An additional 8 kB of on-chip RAM accessible to U* by DMA (LPC2158 only).
n 32 segment ´ 4 backplane LCD controller supports from 1 to 4 backplanes.
n Single 10-bit DAC provides variable *og output.
n Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
n Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities.
n High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
n 100-pin LQFP package with 38 microcontroller I/O pins minimum.
n Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.