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The P89LPC938 is a single-chip microcontroller, available in low cost packages, based on
a high performance processor architecture that executes instructions in two to four clocks,
six times the rate of standard 80C51 devices. Many system-level functions have been
incorporated into the P89LPC938 in order to reduce component count, board space, and
system cost.
2. Features
2.1 Principal features
n 8 kB byte-erasable Flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
n 256-byte RAM data memory and a 512-byte auxiliary on-chip RAM.
n 512-byte customer Data EEPROM on chip allows serialization of devices, storage of
set-up parameters, etc.
n 8-input multiplexed 10-bit A/D converter. Two *og comparators with selectable
inputs and reference source.
n Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a RTC.
n Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
n CCU provides PWM, input capture, and output compare functions.
n High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
n 28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26
I/O pins while using on-chip oscillator and reset options.
a high performance processor architecture that executes instructions in two to four clocks,
six times the rate of standard 80C51 devices. Many system-level functions have been
incorporated into the P89LPC938 in order to reduce component count, board space, and
system cost.
2. Features
2.1 Principal features
n 8 kB byte-erasable Flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
n 256-byte RAM data memory and a 512-byte auxiliary on-chip RAM.
n 512-byte customer Data EEPROM on chip allows serialization of devices, storage of
set-up parameters, etc.
n 8-input multiplexed 10-bit A/D converter. Two *og comparators with selectable
inputs and reference source.
n Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a RTC.
n Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port and SPI communication port.
n CCU provides PWM, input capture, and output compare functions.
n High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
n 28-pin TSSOP, PLCC, and HVQFN packages with 23 I/O pins minimum and up to 26
I/O pins while using on-chip oscillator and reset options.