浙江祥新电子有限公司

A high performance 80C51 CPU provides instruction cycle times of 111 ns to
222 ns for all instructions except multiply and divide when executing at 18 MHz.
This is 6 times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
n 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
n 4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.
n Byte-erase allowing code memory to be used for data storage.
n Flash program operation completes in 2 ms.
n Flash erase operation completes in 2 ms.
n 256-byte RAM data memory.
n Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.
n Real-Time clock that can also be used as a system timer.
n Two *og comparators with selectable inputs and reference source.
n Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
n 400 kHz byte-wide I2C-bus communication port.
n SPI communication port.
n Eight ke*ad interrupt inputs, plus two additional external interrupt inputs.
n Four interrupt priority levels.
n Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog time-out time is selectable from 8 values.
n Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.